An apparatus is disclosed, the apparatus including a branch target cache memory configured to store one or more entries. Each entry of the one or more entries may include an address tag and a corresponding target address. The apparatus may also include a control circuit configured to check for at least one taken branch instruction in a group of one or more instructions fetched using a current address. The control circuit may be further configured to generate an address tag corresponding to the group of one or more instructions using another address used prior to the current address in response to a determination that the group of one or more instructions includes a taken branch instruction. In addition, the control circuit may be configured to store the corresponding address tag and a target address associated with the taken branch instruction in a particular entry in the branch target cache memory.