A processor circuit and an operation method thereof are provided. The processor circuit includes a first alias queue module, a second alias queue module, and a pattern detection module. The pattern detection module is coupled to the first alias queue module and the second alias queue module. When a next sequential instruction pointer value of a store data instruction of the first alias queue module is matched, and a next sequential instruction pointer value of a store address instruction of the second alias queue module is matched, the pattern detection module determines that the load instruction depends on the store data instruction or the store address instruction according to a pattern value corresponding to the store data instruction.