Invention Grant
- Patent Title: Multilevel fault simulations for integrated circuits (IC)
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Application No.: US16140496Application Date: 2018-09-24
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Publication No.: US10747633B2Publication Date: 2020-08-18
- Inventor: Kevin Locker , Sai Ram Dheeraj Lokam , Siva Prasad Kota , Massimo Ceppi , Teo Cupaiuolo
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: G06F11/26
- IPC: G06F11/26 ; G01R31/28 ; G06F30/15 ; G06F30/33 ; G06F30/327 ; G01R31/00 ; G06F117/02

Abstract:
Embodiments include apparatuses, methods, and systems for testing an IC of an in-vehicle system of a CA/AD vehicle includes a storage device and processing circuitry coupled with the storage device. A gate level fault group is provided to include one or more gate level faults of a fault model associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics. A correlated RTL fault group is determined to be associated to a RTL circuit node, where the RTL circuit node of the RTL netlist corresponds to the gate level circuit element. Other embodiments may also be described and claimed.
Public/Granted literature
- US20190050307A1 MULTILEVEL FAULT SIMULATIONS FOR INTEGRATED CIRCUITS (IC) Public/Granted day:2019-02-14
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