Invention Grant
- Patent Title: Methods and systems for patterning of low aspect ratio stacks
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Application No.: US16407042Application Date: 2019-05-08
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Publication No.: US10748769B2Publication Date: 2020-08-18
- Inventor: Elliott Franke , Angelique Raley , Sophie Thibaut
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: TOKYO ELECTRON LIMITED
- Current Assignee: TOKYO ELECTRON LIMITED
- Current Assignee Address: JP Tokyo
- Agency: Rothwell, Figg, Ernst & Manbeck, P.C.
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L21/311 ; H01L21/67 ; H01L21/027 ; H01L21/02

Abstract:
Embodiments of methods and systems for patterning of low aspect ratio stacks are described. In one embodiment, a method may include receiving a substrate comprising a patterned organic planarizing layer (OPL) mask wherein a surface of the OPL mask is exposed, the OPL mask landing on a dielectric layer. The method may also include performing a partial etch of the dielectric layer in a region exposed by the OPL mask. Additionally, the method may include depositing a capping material on a surface of the OPL mask. The method may also include performing a cyclical process of the partial etch of the dielectric layer and deposition of the capping material on a surface of the OPL mask until the dielectric layer is removed to a target depth. In such embodiments, the cyclical process generates an output patterned substrate with a target line edge roughness (LER).
Information query
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