Invention Grant
- Patent Title: Dynamic biasing to mitigate electrical stress in integrated resistors
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Application No.: US16231243Application Date: 2018-12-21
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Publication No.: US10748818B2Publication Date: 2020-08-18
- Inventor: Tathagata Chatterjee , Steven Loveless , James Robert Todd , Andrew Strachan
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Andrew R. Ralston; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L49/02
- IPC: H01L49/02 ; H01L21/8234 ; H01L21/762 ; H01L23/528 ; H01L23/00 ; H01L23/532
Abstract:
In various examples, a method and apparatus are provided to achieve dynamic biasing to mitigate electrical stress. Described examples include a device includes a first resistor portion having a first terminal and a second terminal, and a second resistor portion having a third terminal and a fourth terminal. The device also includes a well in a substrate proximate to the first resistor portion and the second resistor portion and an insulating layer between the well and the first resistor portion and the second resistor portion. The device also includes a transistor having a control terminal coupled to the second terminal of the first resistor portion and the third terminal of the second resistor portion, the transistor having a first current-handling terminal coupled to a first voltage and a second current-handling terminal coupled to a current source and to the well.
Information query
IPC分类:
