Invention Grant
- Patent Title: Packaged semiconductor devices for high voltage with die edge protection
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Application No.: US16120922Application Date: 2018-09-04
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Publication No.: US10748827B2Publication Date: 2020-08-18
- Inventor: Woochan Kim , Vivek Arora , Anindya Poddar
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Dawn Jos; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/29 ; H01L23/00 ; H01L23/495 ; H01L21/78 ; H01L21/56

Abstract:
In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.
Public/Granted literature
- US20200075441A1 PACKAGED SEMICONDUCTOR DEVICES FOR HIGH VOLTAGE WITH DIE EDGE PROTECTION Public/Granted day:2020-03-05
Information query
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