Invention Grant
- Patent Title: Methods of forming semiconductor device structures including staircase structures
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Application No.: US15875407Application Date: 2018-01-19
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Publication No.: US10748918B2Publication Date: 2020-08-18
- Inventor: Toru Tanzawa
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L27/11575
- IPC: H01L27/11575 ; H01L27/11582

Abstract:
A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.
Public/Granted literature
- US20180145029A1 METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES INCLUDING STAIRCASE STRUCTURES Public/Granted day:2018-05-24
Information query
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