- Patent Title: Formation of self-aligned bottom spacer for vertical transistors
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Application No.: US16454587Application Date: 2019-06-27
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Publication No.: US10749012B2Publication Date: 2020-08-18
- Inventor: Ruqiang Bao , Hemanth Jagannathan , Choonghyun Lee , Shogo Mochizuki
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Vazken Alexanian
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L29/66 ; H01L27/092 ; H01L29/06 ; H01L29/423 ; H01L29/786 ; H01L21/8238 ; H01L29/78

Abstract:
A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.
Public/Granted literature
- US20190319114A1 FORMATION OF SELF-ALIGNED BOTTOM SPACER FOR VERTICAL TRANSISTORS Public/Granted day:2019-10-17
Information query
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