Invention Grant
- Patent Title: Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features
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Application No.: US16525348Application Date: 2019-07-29
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Publication No.: US10749014B2Publication Date: 2020-08-18
- Inventor: Che-Cheng Chang , Jr-Jung Lin , Shih-Hao Chen , Chih-Han Lin , Mu-Tsang Lin , Yung-Jung Chang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/762 ; H01L29/78 ; H01L21/311

Abstract:
A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation structure and engaging the fin; and a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack. The semiconductor device further includes a first dielectric layer vertically between the fin and the gate spacer. The semiconductor device further includes a second dielectric layer vertically between the first dielectric layer and the gate spacer, wherein the first and second dielectric layers include different materials, and wherein the second dielectric layer is in physical contact with the gate spacer and the first dielectric layer.
Information query
IPC分类: