Invention Grant
- Patent Title: Large area contacts for small transistors
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Application No.: US15273778Application Date: 2016-09-23
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Publication No.: US10749031B2Publication Date: 2020-08-18
- Inventor: Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-Chen Yeh
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES, Inc. , STMICROELECTRONICS, INC.
- Applicant Address: US NY Armonk US TX Coppell KY
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION,STMICROELECTRONICS, INC.,GLOBALFOUNDRIES, INC
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION,STMICROELECTRONICS, INC.,GLOBALFOUNDRIES, INC
- Current Assignee Address: US NY Armonk US TX Coppell KY
- Agency: Cantor Colburn LLP
- Agent Steven Meyers
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/417 ; H01L29/66 ; H01L29/08 ; H01L29/45 ; H01L21/02 ; H01L21/8234 ; H01L21/768 ; H01L21/285
Abstract:
A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.
Public/Granted literature
- US20170012130A1 LARGE AREA CONTACTS FOR SMALL TRANSISTORS Public/Granted day:2017-01-12
Information query
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