Invention Grant
- Patent Title: ESD protection circuit with passive trigger voltage controlled shut-off
-
Application No.: US15361736Application Date: 2016-11-28
-
Publication No.: US10749336B2Publication Date: 2020-08-18
- Inventor: Krishna Praveen Mysore Rajagopal , Ann Margaret Concannon , Vishwanath Joshi , Aravind Chennimalai Appaswamy , Mariano Dissegna
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Rose Alyssa Keagy; Charles A. Brill; Frank D. Cimino
- Main IPC: H02H9/00
- IPC: H02H9/00 ; H02H9/04 ; H01L27/02

Abstract:
Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.
Public/Granted literature
- US20180152019A1 ESD PROTECTION CIRCUIT WITH PASSIVE TRIGGER VOLTAGE CONTROLLED SHUT-OFF Public/Granted day:2018-05-31
Information query