There are included an error signal generation unit that generates an error signal for adding a burst error to each of an MSB and an LSB of the PAM4 signal in units of clock cycles, an error addition unit that performs an exclusive OR operation on the MSB and the LSB and the error signal and outputs bit strings obtained as a result of the operation, and a calculation unit that calculates the minimum number of clock cycles required for realizing a bit error rate of a desired test signal and the number of burst errors to be added to the MSB and the LSB during a period of the minimum number of the clock cycles.