- Patent Title: Memory chip that suspends transfer phase and resumes transfer phase
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Application No.: US16125298Application Date: 2018-09-07
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Publication No.: US10754553B2Publication Date: 2020-08-25
- Inventor: Shizuka Endo , Riki Suzuki , Yoshihisa Kojima
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@78468d21
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a memory cell array. The controller is configured to control a transfer phase in which a command, an address, and first data are transferred to the memory, and a program phase in which the first data is programmed into the memory cell array by the memory after the transfer phase. The controller is configured to suspend the transfer phase after initiating the transfer phase before completion of the transfer phase, then read second data from the memory, and resume the transfer phase after reading of the second data is completed.
Public/Granted literature
- US20190087101A1 MEMORY SYSTEM Public/Granted day:2019-03-21
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