Invention Grant
- Patent Title: Tracking error-correction parity calculations
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Application No.: US16107187Application Date: 2018-08-21
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Publication No.: US10754726B2Publication Date: 2020-08-25
- Inventor: David Aaron Palmer
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F16/901

Abstract:
Aspects of the present disclosure configure a memory sub-system to track error-correction parity calculations in the memory sub-system. For example, a memory sub-system controller of the memory sub-system can generate and use a first data structure to map one or more data chunks of an open data block to one or more buffers in a set of buffers for temporary storage of partial parity calculation results for the one or more data chunks, and generate and use a second data structure to map one or more data chunks of an open data block to one or more memory locations on non-volatile memory space (implemented by a set of memory components) for persistent storage of partial panty calculation results for the one or more data chunks.
Public/Granted literature
- US20200065186A1 TRACKING ERROR-CORRECTION PARITY CALCULATIONS Public/Granted day:2020-02-27
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