- Patent Title: Dynamic suppression of error detection in processor switch fabric
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Application No.: US15906093Application Date: 2018-02-27
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Publication No.: US10754740B2Publication Date: 2020-08-25
- Inventor: Anis Mahmoud Jarrar , Nancy Hing-Che Amedeo , John F. West
- Applicant: NXP USA, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/16

Abstract:
A processing system tags read and write transaction packets that are functionally safe and suppresses redundant processing and error checking for functionally safe tagged transaction packets. The processing system includes compute elements that are interconnected via an interconnect fabric that includes resources to route operations. The interconnect fabric includes redundant resources to execute the same routing operations and comparator elements to indicate an error in response to detecting a mismatch between the output of a resource and its corresponding duplicate resource. The interconnect fabric selectively activates the duplicate resources and comparator elements in response to a tag associated with a transaction packet indicating that the transaction packet is safety-critical.
Public/Granted literature
- US20190266060A1 DYNAMIC SUPPRESSION OF ERROR DETECTION IN PROCESSOR SWITCH FABRIC Public/Granted day:2019-08-29
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