Invention Grant
- Patent Title: Vertical transistor having a silicided bottom and method for fabricating thereof
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Application No.: US15918741Application Date: 2018-03-12
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Publication No.: US10755937B2Publication Date: 2020-08-25
- Inventor: Zhaoxu Shen , Duohui Bei
- Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
- Applicant Address: CN Shanghai CN Beijing
- Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION,SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
- Current Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION,SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
- Current Assignee Address: CN Shanghai CN Beijing
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@30f0df05
- Main IPC: H01L21/285
- IPC: H01L21/285 ; H01L29/66 ; H01L21/02 ; H01L21/311 ; H01L21/28 ; H01L29/06 ; H01L29/423 ; H01L29/45 ; H01L29/49 ; H01L29/786

Abstract:
A method of manufacturing a semiconductor device includes providing a substrate structure including a substrate and a semiconductor column vertically protruding from the substrate, sequentially forming a first protective layer and a second protective layer on the substrate, etching a portion of the second protective layer to expose a portion of the first protective layer on the substrate and a portion of the first protective layer on an upper surface of the semiconductor column, removing the exposed portion of the first protective layer on the substrate to expose a lower portion of the semiconductor column, removing a remaining portion of the second protective layer, and forming a first contact material layer on the substrate and in contact with the lower portion of the semiconductor column. The first contact material layer in contact with the lower portion of the semiconductor column does not increase the source series resistance.
Public/Granted literature
- US20180294161A1 VERTICAL TRANSISTOR HAVING A SILICIDED BOTTOM AND METHOD FOR FABRICATING THEREOF Public/Granted day:2018-10-11
Information query
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