Invention Grant
- Patent Title: Wafer-level packaging for enhanced performance
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Application No.: US15992613Application Date: 2018-05-30
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Publication No.: US10755992B2Publication Date: 2020-08-25
- Inventor: Julio C. Costa , Merrill Albert Hatcher, Jr. , Peter V. Wright , Jon Chadwick
- Applicant: Qorvo US, Inc.
- Applicant Address: US NC Greensboro
- Assignee: Qorvo US, Inc.
- Current Assignee: Qorvo US, Inc.
- Current Assignee Address: US NC Greensboro
- Agency: Withrow & Terranova, P.L.L.C.
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L23/31 ; H01L21/56 ; H01L21/3105 ; H01L23/00 ; H01L23/50 ; H01L23/29 ; H01L21/78 ; H01L21/762 ; H01L23/367 ; H01L21/311 ; H01L23/544
Abstract:
The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.
Public/Granted literature
- US10658259B2 Wafer-level packaging for enhanced performance Public/Granted day:2020-05-19
Information query
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