Invention Grant
- Patent Title: Optimizing structures to fit into a complete cache line
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Application No.: US16070890Application Date: 2016-02-23
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Publication No.: US10761819B2Publication Date: 2020-09-01
- Inventor: Zhigang Gong , Wenqing Fu , Peng Li , Can Que , Zhiwen Wu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- International Application: PCT/CN2016/074305 WO 20160223
- International Announcement: WO2017/143502 WO 20170831
- Main IPC: G06F8/41
- IPC: G06F8/41
Abstract:
An input data structure of a first size may be converted to a plurality of data structures of a second size smaller than the first size. The data structures of the second size are realigned such that each of the plurality of data structures fits in one cache line. The realigned data structures are compiled for use in a vector machine.
Public/Granted literature
- US20190026088A1 OPTIMIZING STRUCTURES TO FIT INTO A COMPLETE CACHE LINE Public/Granted day:2019-01-24
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