Invention Grant
- Patent Title: Securing conditional speculative instruction execution
-
Application No.: US16028750Application Date: 2018-07-06
-
Publication No.: US10761855B2Publication Date: 2020-09-01
- Inventor: Steven Jeffrey Wallach
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Greenberg Traurig
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/30

Abstract:
A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.
Public/Granted literature
- US20190339977A1 Securing Conditional Speculative Instruction Execution Public/Granted day:2019-11-07
Information query