Invention Grant
- Patent Title: Multi-row wiring member for semiconductor device and method for manufacturing the same
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Application No.: US16196507Application Date: 2018-11-20
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Publication No.: US10763202B2Publication Date: 2020-09-01
- Inventor: Kaoru Hishiki , Ichinori Iidani
- Applicant: Ohkuchi Materials Co., Ltd.
- Applicant Address: JP Kagoshima
- Assignee: OHKUCHI MATERIALS CO., LTD.
- Current Assignee: OHKUCHI MATERIALS CO., LTD.
- Current Assignee Address: JP Kagoshima
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@2c88083a
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K1/18 ; H01L23/49 ; H01L23/498 ; H01L23/50 ; H01L21/56 ; H01L21/48 ; H05K3/10 ; H01L23/31 ; H01L23/00

Abstract:
A multi-row wiring member configured of a plurality of wiring members arrayed in a matrix includes a resin layer, a first plating layer forming internal terminals, a plating layer forming wiring portions and a second plating layer forming external terminals. The first plating layer is formed in the resin layer with lower faces thereof uncovered in a bottom surface of the resin layer. The plating layer forming wiring portions is formed on the first plating layer in the resin layer. The second plating layer is formed in the resin layer on partial areas within areas of the plating layer forming wiring portions, with upper faces thereof being uncovered on a top-surface side of the resin layer. On a bottom-surface side of the resin layer, a metal frame is formed at a margin around an aggregate of individual wiring members arrayed in the matrix.
Public/Granted literature
- US20190139879A1 MULTI-ROW WIRING MEMBER FOR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2019-05-09
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