A latch circuit including: a first inverter having a first pull-up transistor connected between a first power supply node and a first output node, and a first pull-down transistor connected between a second power supply node and the first output node; a second inverter having a second pull-up transistor connected between the first power supply node and a second output node, and a second pull-down transistor connected between the second power supply node and the second output node; a first current control transistor connected between the first pull-up transistor and the first output node; a second current control transistor connected between the second pull-up transistor and the second output node; a third current control transistor connected between the first pull-down transistor and the first output node; and a fourth current control transistor connected between the second pull-down transistor and the second output node.