Invention Grant
- Patent Title: Memory system that carries out soft bit decoding
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Application No.: US16352540Application Date: 2019-03-13
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Publication No.: US10763898B2Publication Date: 2020-09-01
- Inventor: Takuya Haga
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@31504c5
- Main IPC: H03M13/45
- IPC: H03M13/45 ; G11C16/34 ; G11C29/52 ; G11C11/56 ; G06F11/10 ; H03M13/11 ; H03M13/00 ; G11C16/14 ; G11C16/26 ; G11C16/16 ; G11C29/04

Abstract:
A memory system includes a nonvolatile semiconductor memory and a controller. The controller is configured to maintain a plurality of log likelihood ratio (LLR) tables for predicting a value of data read from the nonvolatile semiconductor memory, count a number of times that each of write operations, erase operations, and read operations have been carried out with respect to each unit storage region of the nonvolatile semiconductor memory, determine an order in which the LLR tables are referred to, based on the counted number of the read operations and one of the counted number of the write operations and the counted number of the erase operations, which correspond to a target unit storage region of a read operation, and carry out decoding of data read from the target unit storage region of the read operation, using one of the LLR tables selected according to the determined order.
Public/Granted literature
- US20190215019A1 MEMORY SYSTEM THAT CARRIES OUT SOFT BIT DECODING Public/Granted day:2019-07-11
Information query
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