Invention Grant
- Patent Title: DFE margin test methods and circuits that decouple sample feedback timing
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Application No.: US15165134Application Date: 2016-05-26
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Publication No.: US10764093B2Publication Date: 2020-09-01
- Inventor: Brian S. Leibowitz , Bruno W. Garlepp
- Applicant: Rambus Inc.
- Applicant Address: US CA San Jose
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA San Jose
- Agency: Silicon Edge Law Group LLP
- Agent Arthur J. Behiel
- Main IPC: H04L25/03
- IPC: H04L25/03 ; H04L1/24 ; G01R31/317 ; H04L1/20 ; H04L7/033 ; H04J11/00 ; H04L5/00

Abstract:
Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.
Public/Granted literature
- US20160344577A1 DFE Margin Test Methods and Circuits that Decouple Sample feedback Timing Public/Granted day:2016-11-24
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