Invention Grant
- Patent Title: Caching error checking data for memory having inline storage configurations
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Application No.: US16005427Application Date: 2018-06-11
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Publication No.: US10769013B1Publication Date: 2020-09-08
- Inventor: John M. MacLaren , Landon Laws , Carl Nels Olson , Thomas J. Shepherd
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F12/0802 ; G06F3/06 ; G06F11/22

Abstract:
Various embodiments provide for caching of error checking data for memory having inline storage configurations for primary data and error checking data for the primary data. In particular, various embodiments described herein provide for error checking data caching and cancellation of error checking data read commands for memory having inline storage configurations for primary data and associated error checking data. Additionally, various embodiments described herein provide for combining/canceling of error checking data write commands for memory having inline storage configurations for primary data and associated error checking data.
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