Invention Grant
- Patent Title: Cache line contention
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Application No.: US16182669Application Date: 2018-11-07
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Publication No.: US10769067B2Publication Date: 2020-09-08
- Inventor: Alasdair Grant
- Applicant: Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/0815 ; G06F13/16 ; G06F13/00 ; G06F13/28

Abstract:
A cache interconnect and method of operating a cache interconnect are disclosed. In the cache interconnect snoop circuitry stores a table containing an entry, for each of a plurality of cache lines, comprising a cache line identifier, an indication of a most recent processing element of a plurality of processing elements associated with the cache interconnect to access the cache line, and an indication of a data item in the cache line which was identified by the most recent processing element to be accessed. In response to a request from a requesting processing element of the plurality of processing elements, the request identifying a requested data item, the snoop circuitry determines a requested cache line identifier corresponding to the requested data item and looks up that identifier in the table. When the requested cache line identifier is stored in an identified entry in the table, the snoop circuitry provides, based on the requested data item and the indication of the data item in the table, an indication as to whether the requested data item is the same as the data item in the identified entry.
Public/Granted literature
- US20200142831A1 CACHE LINE CONTENTION Public/Granted day:2020-05-07
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