- Patent Title: Concurrent modification of shared cache line by multiple processors
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Application No.: US15809049Application Date: 2017-11-10
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Publication No.: US10769068B2Publication Date: 2020-09-08
- Inventor: Nicholas C. Matsakis , Craig R. Walters , Jane H. Bartik , Chung-Lung K. Shum , Elpida Tzortzatos
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Heslin Rothenberg Farley & Mesiti P.C.
- Agent William A. Kinnaman, Jr., Esq.; Blanche E. Schiller, Esq.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/084
Abstract:
A shared cache line is concurrently modified by multiple processors of a computing environment. The concurrent modification is performed based, at least, on receiving one or more architected instructions (Fetch due to Non-Coherent Store instructions) that permit multiple processors to concurrently update the shared cache line absent obtaining a lock or having exclusive ownership of the data.
Public/Granted literature
- US20190146916A1 CONCURRENT MODIFICATION OF SHARED CACHE LINE BY MULTIPLE PROCESSORS Public/Granted day:2019-05-16
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