Invention Grant
- Patent Title: Zero-latency pulse density modulation interface with format detection
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Application No.: US16170524Application Date: 2018-10-25
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Publication No.: US10770086B2Publication Date: 2020-09-08
- Inventor: Masoud Farshbaf Zinati , Arun Ramani , Amar Vellanki , Xiaofan Fei
- Applicant: Cirrus Logic International Semiconductor Ltd.
- Applicant Address: US TX Austin
- Assignee: Cirrus Logic, Inc.
- Current Assignee: Cirrus Logic, Inc.
- Current Assignee Address: US TX Austin
- Agency: Jackson Walker L.L.P.
- Main IPC: G10L19/03
- IPC: G10L19/03 ; G10L19/032 ; H03F3/183 ; H03F3/217 ; G10L19/26 ; G10L19/008

Abstract:
A method may include receiving a stream of serial pulse-density modulation (PDM) data representing a first channel of data synchronized with a rising edge of a clock associated with the serial PDM data and a second channel of data synchronized with a falling edge of the clock, wherein each of the first channel of data and the second channel of data include encoded datagrams wherein each encoded datagram comprises more than one digital bit, detecting an invalid state associated with the stream, and responsive to detecting the invalid state, determining boundaries of each encoded datagram of the stream based on where within the stream the invalid state occurred.
Public/Granted literature
- US20190259402A1 ZERO-LATENCY PULSE DENSITY MODULATION INTERFACE WITH FORMAT DETECTION Public/Granted day:2019-08-22
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