Write assist circuit of memory device
Abstract:
a device is disclosed to include a first write assist unit and a second write assist unit. The first write assist unit provides a first operational voltage and a second operational voltage to a memory cell. The second write assist unit provides a third operational voltage and a fourth operational voltage to the memory cell. During a write operation, the first write assist unit further adjusts the first operational voltage or the second operational voltage while the third operational voltage and the fourth operational voltage are at a same voltage level, and the second write assist unit further adjusts the third operational voltage or the fourth operational voltage while the first operational voltage and the second operational voltage are at a same voltage level.
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