Invention Grant
- Patent Title: Method for forming stacked nanowire transistors
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Application No.: US16033401Application Date: 2018-07-12
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Publication No.: US10770290B2Publication Date: 2020-09-08
- Inventor: Tung Ying Lee , Shao-Ming Yu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L29/423 ; H01L29/66 ; H01L29/775 ; H01L29/10 ; H01L29/786 ; H01L29/06 ; H01L21/283 ; H01L29/78

Abstract:
A semiconductor device includes a substrate, a first semiconductor stack including elongated semiconductor features isolated from each other and overlaid in a direction perpendicular to a top surface of the substrate, and a second semiconductor stack including elongated semiconductor features isolated from each other and overlaid in the direction perpendicular to the top surface of the substrate. The second semiconductor stack has different geometric characteristics than the first semiconductor stack. A top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.
Public/Granted literature
- US20180323065A1 Method for Forming Stacked Nanowire Transistors Public/Granted day:2018-11-08
Information query
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