Invention Grant
- Patent Title: Integrated circuit and fabrication method thereof
-
Application No.: US16112955Application Date: 2018-08-27
-
Publication No.: US10770345B2Publication Date: 2020-09-08
- Inventor: Tai-Yen Peng , Chang-Sheng Lin , Chien-Chung Huang , Yu-Shu Chen , Sin-Yi Yang , Chen-Jung Wang , Han-Ting Lin , Chih-Yuan Ting , Jyu-Horng Shieh
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L43/12
- IPC: H01L43/12 ; G11C11/16 ; H01L27/22 ; H01L43/02 ; H01L43/08 ; H01L21/768 ; H01L21/3105 ; H01L27/24
Abstract:
A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
Public/Granted literature
- US20200066580A1 INTEGRATED CIRCUIT AND FABRICATION METHOD THEREOF Public/Granted day:2020-02-27
Information query
IPC分类:
