Invention Grant
- Patent Title: Interconnect structure
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Application No.: US16657169Application Date: 2019-10-18
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Publication No.: US10770347B2Publication Date: 2020-09-08
- Inventor: Daniel C. Edelstein , Son V. Nguyen , Takeshi Nogami , Deepika Priyadarshini , Hosadurga K. Shobha
- Applicant: TESSERA, INC.
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lee & Hayes, P.C.
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/02 ; H01L23/528 ; H01L23/532 ; H01L23/522

Abstract:
Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
Public/Granted literature
- US20200051854A1 INTERCONNECT STRUCTURE Public/Granted day:2020-02-13
Information query
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