Invention Grant
- Patent Title: Integrated circuit with improved resistive region
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Application No.: US16429836Application Date: 2019-06-03
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Publication No.: US10770357B2Publication Date: 2020-09-08
- Inventor: Benoit Froment , Stephan Niel , Arnaud Regnier , Abderrezak Marzaki
- Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
- Applicant Address: FR Crolles FR Rousset
- Assignee: STMicroelectronics (Crolles 2) SAS,STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS,STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Crolles FR Rousset
- Agency: Crowe & Dunlevy
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@626c8c15
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/762 ; H01L21/74 ; H01L27/08 ; H01L49/02 ; H01C7/12 ; H01L21/765 ; H01L29/8605 ; H01L29/06 ; H01L23/522

Abstract:
An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.
Public/Granted literature
- US20190287862A1 INTEGRATED CIRCUIT WITH IMPROVED RESISTIVE REGION Public/Granted day:2019-09-19
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