A chip packaging structure and method, and an electronic device, are provided. The chip packaging structure includes a support, a chip, at least one conductor, and a package for plastic packaging the support, the chip and the conductor. The chip is arranged on an upper surface of the support, a chip pad is formed on the upper surface of the chip, and the chip pad is connected to an external pad of the support by a bonding wire. The conductor is connected to the external pad or a ground pad of the chip pad, and the shortest distance from the conductor to the upper surface of the package is less than the shortest distance from the bonding wire to the upper surface of the package, whereby chip failure caused by static electricity discharge is greatly reduced.