Invention Grant
- Patent Title: Methods of fabricating semiconductor packages including reinforcement top die
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Application No.: US16176806Application Date: 2018-10-31
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Publication No.: US10770445B2Publication Date: 2020-09-08
- Inventor: Kwon Whan Han
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon-si, Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon-si, Gyeonggi-do
- Agency: William Park & Associates Ltd.
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@4dda2d24
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L25/00 ; H01L25/18 ; H01L23/00 ; H01L23/31 ; H01L23/48 ; H01L21/78
Abstract:
A method of fabricating semiconductor packages may include forming stack structures on a base die wafer, disposing a top die wafer on the stack structures, and forming a molding layer filling a space between the base die wafer and the top die wafer.
Public/Granted literature
- US20190259743A1 METHODS OF FABRICATING SEMICONDUCTOR PACKAGES INCLUDING REINFORCEMENT TOP DIE Public/Granted day:2019-08-22
Information query
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