Invention Grant
- Patent Title: Memory array having connections going through control gates
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Application No.: US15457473Application Date: 2017-03-13
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Publication No.: US10770470B2Publication Date: 2020-09-08
- Inventor: Toru Tanzawa , Tamotsu Murakoshi , Deepak Thimmegowda
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L29/66 ; H01L29/792 ; G11C16/04 ; H01L27/11556 ; H01L27/11529 ; H01L27/11548 ; H01L27/11573 ; H01L27/11575 ; H01L27/11582 ; H01L27/11521 ; H01L27/11568

Abstract:
Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.
Public/Granted literature
- US20170250190A1 MEMORY ARRAY HAVING CONNECTIONS GOING THROUGH CONTROL GATES Public/Granted day:2017-08-31
Information query
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