Invention Grant
- Patent Title: Stacked resistive random access memory with integrated access transistor and high density layout
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Application No.: US16368065Application Date: 2019-03-28
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Publication No.: US10770512B1Publication Date: 2020-09-08
- Inventor: Reinaldo Vega , Takashi Ando , Hari Mallela , Li-Wen Hung
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Erik Johnson
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/24 ; G11C13/00

Abstract:
A stacked resistive random access memory (ReRAM) structure is provided. The stacked ReRAM structure includes a channel, a ReRAM cell sub-structure and a contact via sub-structure. The ReRAM cell structure includes ReRAM cell, drain, gate and source layers, which are insulated from one another and respectively disposed in operative contact with the channel. The contact via sub-structures includes first, second, third and fourth contact vias, which are separate from one another. The first contact via is disposed in exclusive operative contact with the ReRAM cell layer. The second contact via is disposed in exclusive operative contact with the drain layer. The third contact via is disposed in exclusive operative contact with the gate layer. The fourth contact via is disposed in exclusive operative contact with the source layer.
Public/Granted literature
- US20200312912A1 STACKED RESISTIVE RANDOM ACCESS MEMORY WITH INTEGRATED ACCESS TRANSISTOR AND HIGH DENSITY LAYOUT Public/Granted day:2020-10-01
Information query
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