Invention Grant
- Patent Title: Gate structure and patterning method for multiple threshold voltages
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Application No.: US16363109Application Date: 2019-03-25
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Publication No.: US10770563B2Publication Date: 2020-09-08
- Inventor: Chung-Liang Cheng , Ziwei Fang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/49
- IPC: H01L29/49 ; H01L27/092 ; H01L29/66 ; H01L27/088 ; H01L29/78 ; H01L21/8238

Abstract:
A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.
Public/Granted literature
- US20200135879A1 Gate Structure and Patterning Method for Multiple Threshold Voltages Public/Granted day:2020-04-30
Information query
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