Invention Grant
- Patent Title: (110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor device
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Application No.: US15225298Application Date: 2016-08-01
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Publication No.: US10770588B2Publication Date: 2020-09-08
- Inventor: Chao-Ching Cheng , Chih-Hsin Ko , Hsingjen Wann
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/45 ; H01L29/51 ; H01L29/66 ; H01L29/04 ; H01L29/20 ; H01L21/28 ; H01L21/308 ; H01L29/06 ; H01L29/49
Abstract:
A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.
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