Invention Grant
- Patent Title: Fabrication method of substrate having electrical interconnection structures
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Application No.: US15867919Application Date: 2018-01-11
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Publication No.: US10774427B2Publication Date: 2020-09-15
- Inventor: Po-Yi Wu , Chun-Hung Lu
- Applicant: Siliconware Precision Industries Co., Ltd.
- Applicant Address: TW Taichung
- Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee: Siliconware Precision Industries Co., Ltd.
- Current Assignee Address: TW Taichung
- Agency: Mintz Levin Cohn Ferris Glovsky and Popeo, P.C.
- Agent Peter F. Corless; Steven M. Jensen
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@f78615 com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@4e1d348f
- Main IPC: H05K3/40
- IPC: H05K3/40 ; C23F1/00 ; H01L23/498 ; H01L21/48 ; H01L23/14

Abstract:
A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.
Public/Granted literature
- US20180135185A1 FABRICATION METHOD OF SUBSTRATE HAVING ELECTRICAL INTERCONNECTION STRUCTURES Public/Granted day:2018-05-17
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