Invention Grant
- Patent Title: Priority addresses for storage cache management
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Application No.: US15982805Application Date: 2018-05-17
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Publication No.: US10776268B2Publication Date: 2020-09-15
- Inventor: In-Soo Yoon , Chandrasekar Sundaresan
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vierra Magen Marcus LLP
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G06F12/0804

Abstract:
Techniques for management of IS memory in a non-volatile storage device, and methods for use therewith, are described herein. The non-volatile storage device can include non-volatile memory, wherein a portion of the non-volatile memory is designated as intermediate storage (IS) memory and another portion of the non-volatile memory is designated as main storage (MS) memory. The IS memory may have lower read and write latencies than the MS memory. A host device may provide priority addresses to a memory controller with an indication that host data having one of the priority addresses is to receive priority to remain in IS memory over other host data.
Public/Granted literature
- US20190324903A1 STORAGE CACHE MANAGEMENT Public/Granted day:2019-10-24
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