Invention Grant
- Patent Title: Method and apparatus to build a monolithic mesh interconnect with structurally heterogenous tiles
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Application No.: US15396522Application Date: 2016-12-31
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Publication No.: US10776309B2Publication Date: 2020-09-15
- Inventor: Rahul Pal , Ishwar Agarwal
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: NDWE, LLP
- Main IPC: H04L12/50
- IPC: H04L12/50 ; G06F15/80 ; G06F15/173
Abstract:
A hetero-mesh architecture is provided to enable varying densities of tile in a multi-core processor. The hetero-mesh architecture includes areas with different tile sizes and wire densities operating and different bandwidths. A split merge switch is utilized between the different parts of the hetero-mesh to enable the sending of packets from tiles in one area of the hetero-mesh to another area of the hetero-mesh while employing a single end to end communication protocol.
Public/Granted literature
- US20180189232A1 METHOD AND APPARATUS TO BUILD A MONOLITHIC MESH INTERCONNECT WITH STRUCTURALLY HETEROGENOUS TILES Public/Granted day:2018-07-05
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