A semiconductor structure includes first and second device regions. The first device region contains an entirety of a first active area of a first logic device, the second device region contains an entirety of a second active area of a second logic device, and the second device region shares a boundary with the first device region. The semiconductor structure also includes a first metal zero pin positioned partially within the first device region, partially within the second device region, and extending across the boundary, and a via contacting the first metal zero pin. A distance from the center of the via to the boundary is less than or equal to a first predetermined distance, and the via is electrically connected to one of the first logic device or the second logic device.