Invention Grant
- Patent Title: Integration of vertical-transport transistors and planar transistors
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Application No.: US15868199Application Date: 2018-01-11
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Publication No.: US10777465B2Publication Date: 2020-09-15
- Inventor: Ruilong Xie , Chun-chen Yeh , Kangguo Cheng , Tenko Yamashita
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Thompson Hine LLP
- Agent Anthony Canale
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/78 ; H01L27/088 ; H01L29/66 ; H01L29/51
Abstract:
Structures including a vertical-transport field-effect transistor and a planar field-effect transistor, and methods of forming such structures. First and second sacrificial fins are respectively formed over first and second areas of the first device region. One or more semiconductor fins of the vertical-transport field-effect transistor are formed over the second device region. A first gate electrode of the planar field-effect transistor, which is arranged on the first device region between the first sacrificial fin and the second sacrificial fin, and a second gate electrode of the vertical-transport field-effect transistor, which is wrapped about the one or more semiconductor fins, are currently formed.
Public/Granted literature
- US20190214307A1 INTEGRATION OF VERTICAL-TRANSPORT TRANSISTORS AND PLANAR TRANSISTORS Public/Granted day:2019-07-11
Information query
IPC分类:
