Invention Grant
- Patent Title: Method of fabricating integrated circuit having staggered conductive features
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Application No.: US16202922Application Date: 2018-11-28
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Publication No.: US10777505B2Publication Date: 2020-09-15
- Inventor: Fong-Yuan Chang , Sheng-Hsiung Chen , Po-Hsiang Huang , Jyun-Hao Chang , Chun-Chen Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L23/528
- IPC: H01L23/528 ; G06F30/39 ; G06F30/392 ; G06F30/394 ; H01L23/522 ; H01L27/118 ; H01L27/02
Abstract:
A method includes using a processor to placing a cell having a first conductive feature and a second conductive feature on an integrated circuit layout. A length of the first conductive feature is extended, by using the processor, to form a staggered configuration. A set of instructions for manufacturing an integrated circuit based upon the integrated circuit layout is generated, and the set of instructions is stored in a non-transitory machine readable storage medium.
Public/Granted literature
- US20190096807A1 METHOD OF FABRICATING INTEGRATED CIRCUIT HAVING STAGGERED CONDUCTIVE FEATURES Public/Granted day:2019-03-28
Information query
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