Invention Grant
- Patent Title: Reliable passivation for integrated circuits
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Application No.: US16448457Application Date: 2019-06-21
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Publication No.: US10777519B2Publication Date: 2020-09-15
- Inventor: Fook Hong Lee , Juan Boon Tan , Ee Jan Khor
- Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee Address: SG Singapore
- Agency: Thompson Hine LLP
- Agent Anthony Canale
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/31 ; H01L23/525 ; H01L23/00 ; G03F1/36 ; H01L23/528 ; H01L23/532 ; G06F30/392 ; G06F30/394 ; G06F30/398

Abstract:
Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.
Public/Granted literature
- US20190312000A1 RELIABLE PASSIVATION FOR INTEGRATED CIRCUITS Public/Granted day:2019-10-10
Information query
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