Invention Grant
- Patent Title: Low voltage (power) junction FET with all-around junction gate
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Application No.: US16512522Application Date: 2019-07-16
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Publication No.: US10777555B2Publication Date: 2020-09-15
- Inventor: Karthik Balakrishnan , Bahman Hekmatshoartabari , Alexander Reznicek , Jeng-Bang Yau
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Agent L. Jeffrey Kelly
- Main IPC: H01L29/808
- IPC: H01L29/808 ; H01L27/092 ; H01L27/112 ; H01L27/06 ; H01L27/098 ; H01L29/08 ; H01L29/06 ; H01L29/66 ; H01L29/786 ; H01L29/423 ; H01L29/10 ; H01L27/085 ; H01L29/04

Abstract:
A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.
Public/Granted literature
- US20190341382A1 LOW VOLTAGE (POWER) JUNCTION FET WITH ALL-AROUND JUNCTION GATE Public/Granted day:2019-11-07
Information query
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