Invention Grant
- Patent Title: RRAM process integration scheme and cell structure with reduced masking operations
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Application No.: US16349255Application Date: 2017-11-13
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Publication No.: US10777608B2Publication Date: 2020-09-15
- Inventor: Zhichao Lu , Brent Steven Haukness
- Applicant: Hefei Reliance Memory Limited
- Applicant Address: CN Hefei
- Assignee: Hefei Reliance Memory Limited
- Current Assignee: Hefei Reliance Memory Limited
- Current Assignee Address: CN Hefei
- Agency: Sheppard Mullin Richter & Hampton LLP
- International Application: PCT/US2017/061393 WO 20171113
- International Announcement: WO2018/089936 WO 20180517
- Main IPC: H01L27/24
- IPC: H01L27/24 ; H01L45/00 ; G11C7/12 ; G11C13/00

Abstract:
Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchable filament. The RRAM further includes a resistive layer disposed above the switching layer and a bit line disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more memory cells along the bit line.
Public/Granted literature
- US20190288037A1 RRAM PROCESS INTEGRATION SCHEME AND CELL STRUCTURE WITH REDUCED MASKING OPERATIONS Public/Granted day:2019-09-19
Information query
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