Invention Grant
- Patent Title: Simulation event reduction and power control during MBIST through clock tree management
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Application No.: US15936999Application Date: 2018-03-27
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Publication No.: US10783299B1Publication Date: 2020-09-22
- Inventor: Steven Lee Gregor , Puneet Arora , Norman Robert Card
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: CADENCE DESIGN SYSTEMS, INC.
- Current Assignee: CADENCE DESIGN SYSTEMS, INC.
- Current Assignee Address: US CA San Jose
- Agency: Tarolli, Sundheim, Covell & Tummino LLP
- Main IPC: G06F30/00
- IPC: G06F30/00 ; G06F30/3312 ; G06F111/20 ; G06F119/12

Abstract:
An exemplary system, method, and computer-accessible medium may be provided, which may include, for example, receiving a design a memory including a plurality MBIST logic paths and a plurality of non-MBIST logic paths, determining particular non-MBIST logic path(s) of the non-MBIST logic paths to deactivate, and deactivating only the particular non-MBIST logic path(s). The particular non-MBIST logic path(s) may be deactivated using a clock signal. A simulation on the memory may be performed while the particular non-MBIST logic path(s) may be deactivated. The particular non-MBIST logic path(s) may be reactivated after the simulation has been performed. The deactivating the particular non-MBIST logic path(s) may include forcing all flip flops in the particular non-MBIST logic path(s) to a known state.
Information query