Invention Grant
- Patent Title: Apparatuses and methods including two transistor-one capacitor memory and for accessing same
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Application No.: US16105631Application Date: 2018-08-20
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Publication No.: US10783951B2Publication Date: 2020-09-22
- Inventor: Christopher J. Kawamura , Scott J. Derner
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C11/24
- IPC: G11C11/24 ; G11C11/4091 ; G11C7/06 ; G11C11/403 ; G11C11/4094 ; G11C11/4097 ; H01L27/108 ; G11C5/02 ; G11C7/18 ; G11C8/16 ; G11C11/4096

Abstract:
Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.
Public/Granted literature
- US10854276B2 Apparatuses and methods including two transistor-one capacitor memory and for accessing same Public/Granted day:2020-12-01
Information query