- Patent Title: Tunable negative bitline write assist and boost attenuation circuit
-
Application No.: US16389489Application Date: 2019-04-19
-
Publication No.: US10783958B2Publication Date: 2020-09-22
- Inventor: Dinesh Chandra , Eswararao Potladhurthi , Dhani Reddy Sreenivasula Reddy , Krishnan S. Rengarajan
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Roberts, Calderon, Safran & Cole, PC
- Agent Steven Meyers; Andrew M. Calderon
- Main IPC: G11C11/419
- IPC: G11C11/419 ; G11C7/12 ; G11C11/412

Abstract:
An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.
Public/Granted literature
- US20190304536A1 TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT Public/Granted day:2019-10-03
Information query
IPC分类: